Fish

Wednesday, November 24, 2010

4 bit Up Counter with Asynchronous reset

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity counter is
 port(C, CLR : in  std_logic;
        Q : out std_logic_vector(3 downto 0));


end counter;

architecture Behavioral of counter is
 signal tmp: std_logic_vector(3 downto 0);

begin

process (C, CLR)
      begin
        if (CLR='1') then
          tmp <= "0000";
        elsif (C'event and C='1')   then
          tmp <= tmp + 1;
        end if;
    end process;
    Q <= tmp;

end Behavioral;