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Sunday, October 17, 2010

8 bit Serial to Parallel Converter

Here is the VHDL code for the 8 bit Serial to Parallel Converter

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SerinParout is

port(
CLKs : in std_logic;
CLKp : out std_logic;
RST  : in std_logic;
Serial1: in std_logic;

Parallel1 : out std_logic_vector(7 downto 0));

end SerinParout;

architecture Behavioral of SerinParout is
signal temp : std_logic_vector(6 downto 0);
signal counter: integer;
begin
 process(RST,CLKs)
 begin
  if RST='1' then
    temp<="0000000";
counter<=0;
CLKp <='0';

  else
     if(CLKs='1' and CLKs'event) then
       if (counter<7) then
           temp(counter)<=Serial1;
           CLKp <='0';
           counter<=counter+1;
       else
           Parallel1<=Serial1&temp;
           CLKp<='1';
           counter<=0;
       end if;
     end if;

end if;
 end process;
end Behavioral;
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