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Sunday, October 17, 2010

8 bit Parallel to Serial Converter

Here is the VHDL code for the 8 bit Parallel to Serial Converter

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;



entity P2S is
port ( Serial_out: out std_logic ;
        clk      : in std_logic;
 Parallel_data: in std_logic_vector(7 downto 0);
 DataReady    : in std_logic);

end P2S;

architecture Behavioral of P2S is

Signal Shreg: std_logic_vector( 7 downto 0);

begin

process( clk)
begin
 if rising_edge(clk) then
    if DataReady='1' then
       Shreg <= Parallel_data;
    else
       Shreg <= Shreg(0)& Shreg(7 downto 1);
    end if;
  end if;
end process;

Serial_out <= Shreg(0);

end Behavioral;